Stage 1 : rien

Stage 2 : - register renaming
	  - use free list to get new destination register (/!\ 4 fifo in para A CHECKER), and update register map
	  - set destination busy
	  - set instruction in active list :
		old dest => previous mapping; 
		log dest => logical register; 
		done => 0

Stage 3 1/2 : -mettre instruction dans queue :
		tag => address in active list;
		Rdy => 3 bits, 1 for each operand;
		OpABC => physical regitser number;
		Dest => physical register of dest

		/!\ Address queue = FIFO

Stage 3 2/2 : -read operand, check busy bit
	      -if all ready, issue instruction to FU, remove from queue ONLY FOR FLOATING POINT

Stage 4, 5, 6 : execute, 1 cycle for each instruction

Stage 7 1/2 : write result, unset busy bit
		remove from active list, remove from queue ONLY FOR ADDRESSES