1. The register file is read in the 2nd of the cycle, because new values are always written in the 1st half of the cycle (integer, fp or loads).
Avantages : 
Disadvantages :

2. Before the renaming, these 5 bits correspond to the number of the logical register (the register indicated on the instruction written by the compiler).
The mapping maps this register to a physical register (which exists on the processor).
As there are 64 physical registers, due to the fact that the processor needs more physical registers than the number of logical ones,
after the renaming, each register is indicated with 6 bits.

3. 
Queues : TODO
Active list : This structure memorizes (in order) all instructions currently in the processor. When the Execution Unit in charge of the instruction has finished executing it,
it sends a signal to the Active List, which graduates it (A VERIFIER). It is similar to the ROB in the course.
Register Map Tables : These structures store both register mappings for integer registers and floating point ones, from physical registers to logical ones.
(A FINIR)

4. TODO

5. TODO

6. There are 12 read ports in the FP busy bits table. This is because each of the 4 instructions decoded each cycle can access this structure, requesting for the status of each of their 3 operands.
There are 16 read ports and 4 write ports in the FP register map table. This is because each of the 4 instructions decoded each cycle needs to know the mapping of (at most) 3 operands and 1 destination registers, 
and each of these instruction needs a new mapping for the result of the operation.