pipeline : bad : control + data hazards, rigid sequencing

Main Dimensions in Renaming :
1. Scope of register renaming Scope of register renaming
2. Layout of the renamed registers
3. Method of register mapping
4. Rename rate Rename rate

Exceptions and Speculation
°Static renaming: Hardware and operating systems cooperatively ignore exceptions
°Poison bits: Mark results as speculative and delay exceptions
°Speculative instructions: Mark instruction as speculative and do not commit the result until speculation is solved

VLIW :
Overcoming Control Dependencies: 
-Predicated Execution 
-Loop Transformations
-Trace Scheduling

Difficult Problems for DBT :
-Self-modifying code
-Precise exceptions
-Address translations, aliasing
-Self-referential code
-Management of translation cache
-Real-time code
-Boot code

Some Problems Connected to DSPs :
°Memory Address Computation
°Special-Purpose Register Allocation
°Multiple Cluster Partitioning and Scheduling
°SIMD Code Selection

Two Problems with AGUs :
°Memory layout (a k a offset assignment) :
How to arrange data in memory in such a way that the typical access sequence can be done with only automatic address updates?
=> hamiltonian path
°Address Register allocation:
How to make all accesses with a minimal number of registers and with only automatic address updates?
=> minimum number of paths

Optimal Code Generation for DFGs
CSE put in the same register

Gain Potentials in Adhoc FUs :
°Exploit constant for logic simplification
°Some operations reduce to wires
°Exploit data parallelism in hardware
°Exploit arithmetic properties for efficient chaining of operations (ex : carry save)

Design Automation for ISE
°Identification of Instruction Set Identification of Instruction Set Extensions => find convex subgraphs that maximize speedup
°Including Architectural State in Instruction Set Extensions => small memories (Decide which pieces of data are best stored locally in the AFU)
°Compiler Technology for Customizable Processors => Predication, Loop Unrolling in Hardware
°Implementing Efficient Data paths in Semicustom Design Flows => get the best implementation in hardware of the operation
°Reconfigurable Computing => ASIC
 / FPGA