alt_sld_fab |

2015.05.01.03:44:59 | Datasheet

Overview

Memory Map

## presplit

altera_super_splitter v14.1

## Parameters
MAX_WIDTH | 25
SEND_WIDTHS | 3 4
RECEIVE_WIDTHS | 24 25
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## splitter

altera_sld_splitter v14.1

presplit | pass | splitter
nodes
sldfabric | clock_0
clock_0
node_0
node_0
clock_1
clock_1
node_1
node_1

## Parameters
FRAGMENTS | {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 1 23} {irq irq out 1 1} {ir_out ir_out out 1 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 2 23} {irq irq out 1 1} {ir_out ir_out out 2 2} } clock clock assign {debug.controlledBy {link_1} } moduleassign {debug.virtualInterface.link_1 {debug.endpointLink {fabric sld index 2} } } } }
EXAMPLE |
ADD_INTERFACE_ASGN | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## jtagpins

altera_jtag_pins_bridge v14.1

## Parameters
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## sldfabric

altera_sld_jtag_hub v14.1

jtagpins | clock | sldfabric
clock
node
node
|  | clock_0 | splitter
|  | clock_0
|  | node_0
|  | node_0
|  | clock_1
|  | clock_1
|  | node_1
|  | node_1
|  | ident | ident
|  | ident_0

## Parameters
DEVICE_FAMILY | CYCLONEIVE
SETTINGS | {mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 prefer_host {} } {mfr_code 70 type_code 34 version 3 instance 0 ir_width 2 prefer_host {} }
COUNT | 2
N_SEL_BITS | 2
N_NODE_IR_BITS | 5
NODE_INFO | 0001100100010000010001100000000000001100000000000110111000000000
COMPILATION_MODE | 0
BROADCAST_FEATURE | 1
FORCE_IR_CAPTURE_FEATURE | 1
FORCE_PRE_1_4_FEATURE | 0
ENABLE_SOFT_CORE_CONTROLLER | 0
CONN_INDEX | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## ident

altera_connection_identification_hub v14.1

sldfabric | ident | ident
ident_0

## Parameters
DESIGN_HASH | 8033407963cc0baa9ea0
COUNT | 1
SETTINGS | {width 4 latency 0}
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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