// qsys_top.v

// Generated using ACDS version 14.1 186 at 2015.05.01.03:42:43

`timescale 1 ps / 1 ps
module qsys_top (
		input  wire [3:0]  buttons_in_port,  //  buttons.in_port
		output wire [3:0]  buttons_out_port, //         .out_port
		input  wire        clk_clk,          //      clk.clk
		output wire        epcs_dclk,        //     epcs.dclk
		output wire        epcs_sce,         //         .sce
		output wire        epcs_sdo,         //         .sdo
		input  wire        epcs_data0,       //         .data0
		input  wire [4:0]  joystick_export,  // joystick.export
		output wire [11:0] leds_SelC_n,      //     leds.SelC_n
		output wire [7:0]  leds_Sel_R,       //         .Sel_R
		output wire [7:0]  leds_Sel_G,       //         .Sel_G
		output wire [7:0]  leds_Sel_B,       //         .Sel_B
		output wire        leds_reset,       //         .reset
		input  wire        reset_reset_n,    //    reset.reset_n
		inout  wire [7:0]  switch0_export,   //  switch0.export
		inout  wire [7:0]  switch1_export    //  switch1.export
	);

	wire  [31:0] nios2_qsys_0_data_master_readdata;                            // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
	wire         nios2_qsys_0_data_master_waitrequest;                         // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
	wire         nios2_qsys_0_data_master_debugaccess;                         // nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
	wire  [17:0] nios2_qsys_0_data_master_address;                             // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
	wire   [3:0] nios2_qsys_0_data_master_byteenable;                          // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
	wire         nios2_qsys_0_data_master_read;                                // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
	wire         nios2_qsys_0_data_master_write;                               // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
	wire  [31:0] nios2_qsys_0_data_master_writedata;                           // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
	wire  [31:0] nios2_qsys_0_instruction_master_readdata;                     // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
	wire         nios2_qsys_0_instruction_master_waitrequest;                  // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
	wire  [17:0] nios2_qsys_0_instruction_master_address;                      // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
	wire         nios2_qsys_0_instruction_master_read;                         // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
	wire         nios2_qsys_0_instruction_master_readdatavalid;                // mm_interconnect_0:nios2_qsys_0_instruction_master_readdatavalid -> nios2_qsys_0:i_readdatavalid
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect;   // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata;     // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest;  // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address;      // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;         // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;        // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata;    // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
	wire  [31:0] mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_readdata;    // fullrgb_96led_0:as0_rddata -> mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_readdata
	wire         mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_waitrequest; // fullrgb_96led_0:as0_waitrequest -> mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_waitrequest
	wire   [6:0] mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_address;     // mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_address -> fullrgb_96led_0:as0_address
	wire         mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_read;        // mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_read -> fullrgb_96led_0:as0_read
	wire         mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_write;       // mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_write -> fullrgb_96led_0:as0_write
	wire  [31:0] mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_writedata;   // mm_interconnect_0:fullrgb_96led_0_avalon_slave_0_writedata -> fullrgb_96led_0:as0_wrdata
	wire  [31:0] mm_interconnect_0_sysid_qsys_0_control_slave_readdata;        // sysid_qsys_0:readdata -> mm_interconnect_0:sysid_qsys_0_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_0_control_slave_address;         // mm_interconnect_0:sysid_qsys_0_control_slave_address -> sysid_qsys_0:address
	wire  [31:0] mm_interconnect_0_counter_0_control_slave_readdata;           // counter_0:readdata -> mm_interconnect_0:counter_0_control_slave_readdata
	wire   [2:0] mm_interconnect_0_counter_0_control_slave_address;            // mm_interconnect_0:counter_0_control_slave_address -> counter_0:address
	wire         mm_interconnect_0_counter_0_control_slave_begintransfer;      // mm_interconnect_0:counter_0_control_slave_begintransfer -> counter_0:begintransfer
	wire         mm_interconnect_0_counter_0_control_slave_write;              // mm_interconnect_0:counter_0_control_slave_write -> counter_0:write
	wire  [31:0] mm_interconnect_0_counter_0_control_slave_writedata;          // mm_interconnect_0:counter_0_control_slave_writedata -> counter_0:writedata
	wire         mm_interconnect_0_epcs_epcs_control_port_chipselect;          // mm_interconnect_0:epcs_epcs_control_port_chipselect -> epcs:chipselect
	wire  [31:0] mm_interconnect_0_epcs_epcs_control_port_readdata;            // epcs:readdata -> mm_interconnect_0:epcs_epcs_control_port_readdata
	wire   [8:0] mm_interconnect_0_epcs_epcs_control_port_address;             // mm_interconnect_0:epcs_epcs_control_port_address -> epcs:address
	wire         mm_interconnect_0_epcs_epcs_control_port_read;                // mm_interconnect_0:epcs_epcs_control_port_read -> epcs:read_n
	wire         mm_interconnect_0_epcs_epcs_control_port_write;               // mm_interconnect_0:epcs_epcs_control_port_write -> epcs:write_n
	wire  [31:0] mm_interconnect_0_epcs_epcs_control_port_writedata;           // mm_interconnect_0:epcs_epcs_control_port_writedata -> epcs:writedata
	wire  [31:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata;    // nios2_qsys_0:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_readdata
	wire         mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest; // nios2_qsys_0:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_waitrequest
	wire         mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address;     // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_address -> nios2_qsys_0:jtag_debug_module_address
	wire         mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read;        // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_read -> nios2_qsys_0:jtag_debug_module_read
	wire   [3:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable;  // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
	wire         mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write;       // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_write -> nios2_qsys_0:jtag_debug_module_write
	wire  [31:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata;   // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_writedata -> nios2_qsys_0:jtag_debug_module_writedata
	wire         mm_interconnect_0_onchip_memory_s1_chipselect;                // mm_interconnect_0:onchip_memory_s1_chipselect -> onchip_memory:chipselect
	wire  [31:0] mm_interconnect_0_onchip_memory_s1_readdata;                  // onchip_memory:readdata -> mm_interconnect_0:onchip_memory_s1_readdata
	wire  [13:0] mm_interconnect_0_onchip_memory_s1_address;                   // mm_interconnect_0:onchip_memory_s1_address -> onchip_memory:address
	wire   [3:0] mm_interconnect_0_onchip_memory_s1_byteenable;                // mm_interconnect_0:onchip_memory_s1_byteenable -> onchip_memory:byteenable
	wire         mm_interconnect_0_onchip_memory_s1_write;                     // mm_interconnect_0:onchip_memory_s1_write -> onchip_memory:write
	wire  [31:0] mm_interconnect_0_onchip_memory_s1_writedata;                 // mm_interconnect_0:onchip_memory_s1_writedata -> onchip_memory:writedata
	wire         mm_interconnect_0_onchip_memory_s1_clken;                     // mm_interconnect_0:onchip_memory_s1_clken -> onchip_memory:clken
	wire         mm_interconnect_0_buttons_s1_chipselect;                      // mm_interconnect_0:buttons_s1_chipselect -> buttons:chipselect
	wire  [31:0] mm_interconnect_0_buttons_s1_readdata;                        // buttons:readdata -> mm_interconnect_0:buttons_s1_readdata
	wire   [1:0] mm_interconnect_0_buttons_s1_address;                         // mm_interconnect_0:buttons_s1_address -> buttons:address
	wire         mm_interconnect_0_buttons_s1_write;                           // mm_interconnect_0:buttons_s1_write -> buttons:write_n
	wire  [31:0] mm_interconnect_0_buttons_s1_writedata;                       // mm_interconnect_0:buttons_s1_writedata -> buttons:writedata
	wire         mm_interconnect_0_switch0_s1_chipselect;                      // mm_interconnect_0:switch0_s1_chipselect -> switch0:chipselect
	wire  [31:0] mm_interconnect_0_switch0_s1_readdata;                        // switch0:readdata -> mm_interconnect_0:switch0_s1_readdata
	wire   [1:0] mm_interconnect_0_switch0_s1_address;                         // mm_interconnect_0:switch0_s1_address -> switch0:address
	wire         mm_interconnect_0_switch0_s1_write;                           // mm_interconnect_0:switch0_s1_write -> switch0:write_n
	wire  [31:0] mm_interconnect_0_switch0_s1_writedata;                       // mm_interconnect_0:switch0_s1_writedata -> switch0:writedata
	wire         mm_interconnect_0_switch1_s1_chipselect;                      // mm_interconnect_0:switch1_s1_chipselect -> switch1:chipselect
	wire  [31:0] mm_interconnect_0_switch1_s1_readdata;                        // switch1:readdata -> mm_interconnect_0:switch1_s1_readdata
	wire   [1:0] mm_interconnect_0_switch1_s1_address;                         // mm_interconnect_0:switch1_s1_address -> switch1:address
	wire         mm_interconnect_0_switch1_s1_write;                           // mm_interconnect_0:switch1_s1_write -> switch1:write_n
	wire  [31:0] mm_interconnect_0_switch1_s1_writedata;                       // mm_interconnect_0:switch1_s1_writedata -> switch1:writedata
	wire         mm_interconnect_0_timer_0_s1_chipselect;                      // mm_interconnect_0:timer_0_s1_chipselect -> timer_0:chipselect
	wire  [15:0] mm_interconnect_0_timer_0_s1_readdata;                        // timer_0:readdata -> mm_interconnect_0:timer_0_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_0_s1_address;                         // mm_interconnect_0:timer_0_s1_address -> timer_0:address
	wire         mm_interconnect_0_timer_0_s1_write;                           // mm_interconnect_0:timer_0_s1_write -> timer_0:write_n
	wire  [15:0] mm_interconnect_0_timer_0_s1_writedata;                       // mm_interconnect_0:timer_0_s1_writedata -> timer_0:writedata
	wire         mm_interconnect_0_joystick_s1_chipselect;                     // mm_interconnect_0:joystick_s1_chipselect -> joystick:chipselect
	wire  [31:0] mm_interconnect_0_joystick_s1_readdata;                       // joystick:readdata -> mm_interconnect_0:joystick_s1_readdata
	wire   [1:0] mm_interconnect_0_joystick_s1_address;                        // mm_interconnect_0:joystick_s1_address -> joystick:address
	wire         mm_interconnect_0_joystick_s1_write;                          // mm_interconnect_0:joystick_s1_write -> joystick:write_n
	wire  [31:0] mm_interconnect_0_joystick_s1_writedata;                      // mm_interconnect_0:joystick_s1_writedata -> joystick:writedata
	wire         mm_interconnect_0_timer_1_s1_chipselect;                      // mm_interconnect_0:timer_1_s1_chipselect -> timer_1:chipselect
	wire  [15:0] mm_interconnect_0_timer_1_s1_readdata;                        // timer_1:readdata -> mm_interconnect_0:timer_1_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_1_s1_address;                         // mm_interconnect_0:timer_1_s1_address -> timer_1:address
	wire         mm_interconnect_0_timer_1_s1_write;                           // mm_interconnect_0:timer_1_s1_write -> timer_1:write_n
	wire  [15:0] mm_interconnect_0_timer_1_s1_writedata;                       // mm_interconnect_0:timer_1_s1_writedata -> timer_1:writedata
	wire         irq_mapper_receiver0_irq;                                     // buttons:irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                     // timer_0:irq -> irq_mapper:receiver1_irq
	wire         irq_mapper_receiver2_irq;                                     // jtag_uart_0:av_irq -> irq_mapper:receiver2_irq
	wire         irq_mapper_receiver3_irq;                                     // epcs:irq -> irq_mapper:receiver3_irq
	wire         irq_mapper_receiver4_irq;                                     // joystick:irq -> irq_mapper:receiver4_irq
	wire         irq_mapper_receiver5_irq;                                     // timer_1:irq -> irq_mapper:receiver5_irq
	wire  [31:0] nios2_qsys_0_d_irq_irq;                                       // irq_mapper:sender_irq -> nios2_qsys_0:d_irq
	wire         rst_controller_reset_out_reset;                               // rst_controller:reset_out -> [buttons:reset_n, counter_0:reset_n, epcs:reset_n, fullrgb_96led_0:reset, irq_mapper:reset, joystick:reset_n, jtag_uart_0:rst_n, mm_interconnect_0:nios2_qsys_0_reset_n_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory:reset, rst_translator:in_reset, switch0:reset_n, switch1:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n, timer_1:reset_n]
	wire         rst_controller_reset_out_reset_req;                           // rst_controller:reset_req -> [epcs:reset_req, nios2_qsys_0:reset_req, onchip_memory:reset_req, rst_translator:reset_req_in]
	wire         nios2_qsys_0_jtag_debug_module_reset_reset;                   // nios2_qsys_0:jtag_debug_module_resetrequest -> rst_controller:reset_in1

	qsys_top_buttons buttons (
		.clk        (clk_clk),                                 //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_buttons_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_buttons_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_buttons_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_buttons_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_buttons_s1_readdata),   //                    .readdata
		.in_port    (buttons_in_port),                         // external_connection.export
		.out_port   (buttons_out_port),                        //                    .export
		.irq        (irq_mapper_receiver0_irq)                 //                 irq.irq
	);

	qsys_top_counter_0 counter_0 (
		.clk           (clk_clk),                                                 //           clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                         //         reset.reset_n
		.address       (mm_interconnect_0_counter_0_control_slave_address),       // control_slave.address
		.begintransfer (mm_interconnect_0_counter_0_control_slave_begintransfer), //              .begintransfer
		.readdata      (mm_interconnect_0_counter_0_control_slave_readdata),      //              .readdata
		.write         (mm_interconnect_0_counter_0_control_slave_write),         //              .write
		.writedata     (mm_interconnect_0_counter_0_control_slave_writedata)      //              .writedata
	);

	qsys_top_epcs epcs (
		.clk           (clk_clk),                                             //               clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                     //             reset.reset_n
		.reset_req     (rst_controller_reset_out_reset_req),                  //                  .reset_req
		.address       (mm_interconnect_0_epcs_epcs_control_port_address),    // epcs_control_port.address
		.chipselect    (mm_interconnect_0_epcs_epcs_control_port_chipselect), //                  .chipselect
		.dataavailable (),                                                    //                  .dataavailable
		.endofpacket   (),                                                    //                  .endofpacket
		.read_n        (~mm_interconnect_0_epcs_epcs_control_port_read),      //                  .read_n
		.readdata      (mm_interconnect_0_epcs_epcs_control_port_readdata),   //                  .readdata
		.readyfordata  (),                                                    //                  .readyfordata
		.write_n       (~mm_interconnect_0_epcs_epcs_control_port_write),     //                  .write_n
		.writedata     (mm_interconnect_0_epcs_epcs_control_port_writedata),  //                  .writedata
		.irq           (irq_mapper_receiver3_irq),                            //               irq.irq
		.dclk          (epcs_dclk),                                           //          external.export
		.sce           (epcs_sce),                                            //                  .export
		.sdo           (epcs_sdo),                                            //                  .export
		.data0         (epcs_data0)                                           //                  .export
	);

	if_fullrgb_led96 fullrgb_96led_0 (
		.clk             (clk_clk),                                                      //          clock.clk
		.reset           (rst_controller_reset_out_reset),                               //          reset.reset
		.as0_wrdata      (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_writedata),   // avalon_slave_0.writedata
		.as0_address     (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_address),     //               .address
		.as0_write       (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_write),       //               .write
		.as0_rddata      (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_readdata),    //               .readdata
		.as0_read        (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_read),        //               .read
		.as0_waitrequest (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_waitrequest), //               .waitrequest
		.LED_SelC_n      (leds_SelC_n),                                                  //           LEDs.export
		.LED_Sel_R       (leds_Sel_R),                                                   //               .export
		.LED_Sel_G       (leds_Sel_G),                                                   //               .export
		.LED_Sel_B       (leds_Sel_B),                                                   //               .export
		.LED_reset       (leds_reset)                                                    //               .export
	);

	qsys_top_joystick joystick (
		.clk        (clk_clk),                                  //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),          //               reset.reset_n
		.address    (mm_interconnect_0_joystick_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_joystick_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_joystick_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_joystick_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_joystick_s1_readdata),   //                    .readdata
		.in_port    (joystick_export),                          // external_connection.export
		.irq        (irq_mapper_receiver4_irq)                  //                 irq.irq
	);

	qsys_top_jtag_uart_0 jtag_uart_0 (
		.clk            (clk_clk),                                                     //               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                             //             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect),  // avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address),     //                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read),       //                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata),    //                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write),      //                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata),   //                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), //                  .waitrequest
		.av_irq         (irq_mapper_receiver2_irq)                                     //               irq.irq
	);

	qsys_top_nios2_qsys_0 nios2_qsys_0 (
		.clk                                   (clk_clk),                                                      //                       clk.clk
		.reset_n                               (~rst_controller_reset_out_reset),                              //                   reset_n.reset_n
		.reset_req                             (rst_controller_reset_out_reset_req),                           //                          .reset_req
		.d_address                             (nios2_qsys_0_data_master_address),                             //               data_master.address
		.d_byteenable                          (nios2_qsys_0_data_master_byteenable),                          //                          .byteenable
		.d_read                                (nios2_qsys_0_data_master_read),                                //                          .read
		.d_readdata                            (nios2_qsys_0_data_master_readdata),                            //                          .readdata
		.d_waitrequest                         (nios2_qsys_0_data_master_waitrequest),                         //                          .waitrequest
		.d_write                               (nios2_qsys_0_data_master_write),                               //                          .write
		.d_writedata                           (nios2_qsys_0_data_master_writedata),                           //                          .writedata
		.jtag_debug_module_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess),                         //                          .debugaccess
		.i_address                             (nios2_qsys_0_instruction_master_address),                      //        instruction_master.address
		.i_read                                (nios2_qsys_0_instruction_master_read),                         //                          .read
		.i_readdata                            (nios2_qsys_0_instruction_master_readdata),                     //                          .readdata
		.i_waitrequest                         (nios2_qsys_0_instruction_master_waitrequest),                  //                          .waitrequest
		.i_readdatavalid                       (nios2_qsys_0_instruction_master_readdatavalid),                //                          .readdatavalid
		.d_irq                                 (nios2_qsys_0_d_irq_irq),                                       //                     d_irq.irq
		.jtag_debug_module_resetrequest        (nios2_qsys_0_jtag_debug_module_reset_reset),                   //   jtag_debug_module_reset.reset
		.jtag_debug_module_address             (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address),     //         jtag_debug_module.address
		.jtag_debug_module_byteenable          (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable),  //                          .byteenable
		.jtag_debug_module_debugaccess         (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess), //                          .debugaccess
		.jtag_debug_module_read                (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read),        //                          .read
		.jtag_debug_module_readdata            (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata),    //                          .readdata
		.jtag_debug_module_waitrequest         (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest), //                          .waitrequest
		.jtag_debug_module_write               (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write),       //                          .write
		.jtag_debug_module_writedata           (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata),   //                          .writedata
		.no_ci_readra                          ()                                                              // custom_instruction_master.readra
	);

	qsys_top_onchip_memory onchip_memory (
		.clk        (clk_clk),                                       //   clk1.clk
		.address    (mm_interconnect_0_onchip_memory_s1_address),    //     s1.address
		.clken      (mm_interconnect_0_onchip_memory_s1_clken),      //       .clken
		.chipselect (mm_interconnect_0_onchip_memory_s1_chipselect), //       .chipselect
		.write      (mm_interconnect_0_onchip_memory_s1_write),      //       .write
		.readdata   (mm_interconnect_0_onchip_memory_s1_readdata),   //       .readdata
		.writedata  (mm_interconnect_0_onchip_memory_s1_writedata),  //       .writedata
		.byteenable (mm_interconnect_0_onchip_memory_s1_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset),                // reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)             //       .reset_req
	);

	qsys_top_switch0 switch0 (
		.clk        (clk_clk),                                 //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_switch0_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_switch0_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_switch0_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_switch0_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_switch0_s1_readdata),   //                    .readdata
		.bidir_port (switch0_export)                           // external_connection.export
	);

	qsys_top_switch0 switch1 (
		.clk        (clk_clk),                                 //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_switch1_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_switch1_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_switch1_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_switch1_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_switch1_s1_readdata),   //                    .readdata
		.bidir_port (switch1_export)                           // external_connection.export
	);

	qsys_top_sysid_qsys_0 sysid_qsys_0 (
		.clock    (clk_clk),                                               //           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                       //         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_0_control_slave_readdata), // control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_0_control_slave_address)   //              .address
	);

	qsys_top_timer_0 timer_0 (
		.clk        (clk_clk),                                 //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         // reset.reset_n
		.address    (mm_interconnect_0_timer_0_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_timer_0_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_timer_0_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_timer_0_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_timer_0_s1_write),     //      .write_n
		.irq        (irq_mapper_receiver1_irq)                 //   irq.irq
	);

	qsys_top_timer_0 timer_1 (
		.clk        (clk_clk),                                 //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         // reset.reset_n
		.address    (mm_interconnect_0_timer_1_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_timer_1_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_timer_1_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_timer_1_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_timer_1_s1_write),     //      .write_n
		.irq        (irq_mapper_receiver5_irq)                 //   irq.irq
	);

	qsys_top_mm_interconnect_0 mm_interconnect_0 (
		.clk_0_clk_clk                                    (clk_clk),                                                      //                                  clk_0_clk.clk
		.nios2_qsys_0_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                               // nios2_qsys_0_reset_n_reset_bridge_in_reset.reset
		.nios2_qsys_0_data_master_address                 (nios2_qsys_0_data_master_address),                             //                   nios2_qsys_0_data_master.address
		.nios2_qsys_0_data_master_waitrequest             (nios2_qsys_0_data_master_waitrequest),                         //                                           .waitrequest
		.nios2_qsys_0_data_master_byteenable              (nios2_qsys_0_data_master_byteenable),                          //                                           .byteenable
		.nios2_qsys_0_data_master_read                    (nios2_qsys_0_data_master_read),                                //                                           .read
		.nios2_qsys_0_data_master_readdata                (nios2_qsys_0_data_master_readdata),                            //                                           .readdata
		.nios2_qsys_0_data_master_write                   (nios2_qsys_0_data_master_write),                               //                                           .write
		.nios2_qsys_0_data_master_writedata               (nios2_qsys_0_data_master_writedata),                           //                                           .writedata
		.nios2_qsys_0_data_master_debugaccess             (nios2_qsys_0_data_master_debugaccess),                         //                                           .debugaccess
		.nios2_qsys_0_instruction_master_address          (nios2_qsys_0_instruction_master_address),                      //            nios2_qsys_0_instruction_master.address
		.nios2_qsys_0_instruction_master_waitrequest      (nios2_qsys_0_instruction_master_waitrequest),                  //                                           .waitrequest
		.nios2_qsys_0_instruction_master_read             (nios2_qsys_0_instruction_master_read),                         //                                           .read
		.nios2_qsys_0_instruction_master_readdata         (nios2_qsys_0_instruction_master_readdata),                     //                                           .readdata
		.nios2_qsys_0_instruction_master_readdatavalid    (nios2_qsys_0_instruction_master_readdatavalid),                //                                           .readdatavalid
		.buttons_s1_address                               (mm_interconnect_0_buttons_s1_address),                         //                                 buttons_s1.address
		.buttons_s1_write                                 (mm_interconnect_0_buttons_s1_write),                           //                                           .write
		.buttons_s1_readdata                              (mm_interconnect_0_buttons_s1_readdata),                        //                                           .readdata
		.buttons_s1_writedata                             (mm_interconnect_0_buttons_s1_writedata),                       //                                           .writedata
		.buttons_s1_chipselect                            (mm_interconnect_0_buttons_s1_chipselect),                      //                                           .chipselect
		.counter_0_control_slave_address                  (mm_interconnect_0_counter_0_control_slave_address),            //                    counter_0_control_slave.address
		.counter_0_control_slave_write                    (mm_interconnect_0_counter_0_control_slave_write),              //                                           .write
		.counter_0_control_slave_readdata                 (mm_interconnect_0_counter_0_control_slave_readdata),           //                                           .readdata
		.counter_0_control_slave_writedata                (mm_interconnect_0_counter_0_control_slave_writedata),          //                                           .writedata
		.counter_0_control_slave_begintransfer            (mm_interconnect_0_counter_0_control_slave_begintransfer),      //                                           .begintransfer
		.epcs_epcs_control_port_address                   (mm_interconnect_0_epcs_epcs_control_port_address),             //                     epcs_epcs_control_port.address
		.epcs_epcs_control_port_write                     (mm_interconnect_0_epcs_epcs_control_port_write),               //                                           .write
		.epcs_epcs_control_port_read                      (mm_interconnect_0_epcs_epcs_control_port_read),                //                                           .read
		.epcs_epcs_control_port_readdata                  (mm_interconnect_0_epcs_epcs_control_port_readdata),            //                                           .readdata
		.epcs_epcs_control_port_writedata                 (mm_interconnect_0_epcs_epcs_control_port_writedata),           //                                           .writedata
		.epcs_epcs_control_port_chipselect                (mm_interconnect_0_epcs_epcs_control_port_chipselect),          //                                           .chipselect
		.fullrgb_96led_0_avalon_slave_0_address           (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_address),     //             fullrgb_96led_0_avalon_slave_0.address
		.fullrgb_96led_0_avalon_slave_0_write             (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_write),       //                                           .write
		.fullrgb_96led_0_avalon_slave_0_read              (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_read),        //                                           .read
		.fullrgb_96led_0_avalon_slave_0_readdata          (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_readdata),    //                                           .readdata
		.fullrgb_96led_0_avalon_slave_0_writedata         (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_writedata),   //                                           .writedata
		.fullrgb_96led_0_avalon_slave_0_waitrequest       (mm_interconnect_0_fullrgb_96led_0_avalon_slave_0_waitrequest), //                                           .waitrequest
		.joystick_s1_address                              (mm_interconnect_0_joystick_s1_address),                        //                                joystick_s1.address
		.joystick_s1_write                                (mm_interconnect_0_joystick_s1_write),                          //                                           .write
		.joystick_s1_readdata                             (mm_interconnect_0_joystick_s1_readdata),                       //                                           .readdata
		.joystick_s1_writedata                            (mm_interconnect_0_joystick_s1_writedata),                      //                                           .writedata
		.joystick_s1_chipselect                           (mm_interconnect_0_joystick_s1_chipselect),                     //                                           .chipselect
		.jtag_uart_0_avalon_jtag_slave_address            (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address),      //              jtag_uart_0_avalon_jtag_slave.address
		.jtag_uart_0_avalon_jtag_slave_write              (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write),        //                                           .write
		.jtag_uart_0_avalon_jtag_slave_read               (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read),         //                                           .read
		.jtag_uart_0_avalon_jtag_slave_readdata           (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata),     //                                           .readdata
		.jtag_uart_0_avalon_jtag_slave_writedata          (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata),    //                                           .writedata
		.jtag_uart_0_avalon_jtag_slave_waitrequest        (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest),  //                                           .waitrequest
		.jtag_uart_0_avalon_jtag_slave_chipselect         (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect),   //                                           .chipselect
		.nios2_qsys_0_jtag_debug_module_address           (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address),     //             nios2_qsys_0_jtag_debug_module.address
		.nios2_qsys_0_jtag_debug_module_write             (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write),       //                                           .write
		.nios2_qsys_0_jtag_debug_module_read              (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read),        //                                           .read
		.nios2_qsys_0_jtag_debug_module_readdata          (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata),    //                                           .readdata
		.nios2_qsys_0_jtag_debug_module_writedata         (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata),   //                                           .writedata
		.nios2_qsys_0_jtag_debug_module_byteenable        (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable),  //                                           .byteenable
		.nios2_qsys_0_jtag_debug_module_waitrequest       (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest), //                                           .waitrequest
		.nios2_qsys_0_jtag_debug_module_debugaccess       (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess), //                                           .debugaccess
		.onchip_memory_s1_address                         (mm_interconnect_0_onchip_memory_s1_address),                   //                           onchip_memory_s1.address
		.onchip_memory_s1_write                           (mm_interconnect_0_onchip_memory_s1_write),                     //                                           .write
		.onchip_memory_s1_readdata                        (mm_interconnect_0_onchip_memory_s1_readdata),                  //                                           .readdata
		.onchip_memory_s1_writedata                       (mm_interconnect_0_onchip_memory_s1_writedata),                 //                                           .writedata
		.onchip_memory_s1_byteenable                      (mm_interconnect_0_onchip_memory_s1_byteenable),                //                                           .byteenable
		.onchip_memory_s1_chipselect                      (mm_interconnect_0_onchip_memory_s1_chipselect),                //                                           .chipselect
		.onchip_memory_s1_clken                           (mm_interconnect_0_onchip_memory_s1_clken),                     //                                           .clken
		.switch0_s1_address                               (mm_interconnect_0_switch0_s1_address),                         //                                 switch0_s1.address
		.switch0_s1_write                                 (mm_interconnect_0_switch0_s1_write),                           //                                           .write
		.switch0_s1_readdata                              (mm_interconnect_0_switch0_s1_readdata),                        //                                           .readdata
		.switch0_s1_writedata                             (mm_interconnect_0_switch0_s1_writedata),                       //                                           .writedata
		.switch0_s1_chipselect                            (mm_interconnect_0_switch0_s1_chipselect),                      //                                           .chipselect
		.switch1_s1_address                               (mm_interconnect_0_switch1_s1_address),                         //                                 switch1_s1.address
		.switch1_s1_write                                 (mm_interconnect_0_switch1_s1_write),                           //                                           .write
		.switch1_s1_readdata                              (mm_interconnect_0_switch1_s1_readdata),                        //                                           .readdata
		.switch1_s1_writedata                             (mm_interconnect_0_switch1_s1_writedata),                       //                                           .writedata
		.switch1_s1_chipselect                            (mm_interconnect_0_switch1_s1_chipselect),                      //                                           .chipselect
		.sysid_qsys_0_control_slave_address               (mm_interconnect_0_sysid_qsys_0_control_slave_address),         //                 sysid_qsys_0_control_slave.address
		.sysid_qsys_0_control_slave_readdata              (mm_interconnect_0_sysid_qsys_0_control_slave_readdata),        //                                           .readdata
		.timer_0_s1_address                               (mm_interconnect_0_timer_0_s1_address),                         //                                 timer_0_s1.address
		.timer_0_s1_write                                 (mm_interconnect_0_timer_0_s1_write),                           //                                           .write
		.timer_0_s1_readdata                              (mm_interconnect_0_timer_0_s1_readdata),                        //                                           .readdata
		.timer_0_s1_writedata                             (mm_interconnect_0_timer_0_s1_writedata),                       //                                           .writedata
		.timer_0_s1_chipselect                            (mm_interconnect_0_timer_0_s1_chipselect),                      //                                           .chipselect
		.timer_1_s1_address                               (mm_interconnect_0_timer_1_s1_address),                         //                                 timer_1_s1.address
		.timer_1_s1_write                                 (mm_interconnect_0_timer_1_s1_write),                           //                                           .write
		.timer_1_s1_readdata                              (mm_interconnect_0_timer_1_s1_readdata),                        //                                           .readdata
		.timer_1_s1_writedata                             (mm_interconnect_0_timer_1_s1_writedata),                       //                                           .writedata
		.timer_1_s1_chipselect                            (mm_interconnect_0_timer_1_s1_chipselect)                       //                                           .chipselect
	);

	qsys_top_irq_mapper irq_mapper (
		.clk           (clk_clk),                        //       clk.clk
		.reset         (rst_controller_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),       // receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),       // receiver2.irq
		.receiver3_irq (irq_mapper_receiver3_irq),       // receiver3.irq
		.receiver4_irq (irq_mapper_receiver4_irq),       // receiver4.irq
		.receiver5_irq (irq_mapper_receiver5_irq),       // receiver5.irq
		.sender_irq    (nios2_qsys_0_d_irq_irq)          //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                             // reset_in0.reset
		.reset_in1      (nios2_qsys_0_jtag_debug_module_reset_reset), // reset_in1.reset
		.clk            (clk_clk),                                    //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),             // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req),         //          .reset_req
		.reset_req_in0  (1'b0),                                       // (terminated)
		.reset_req_in1  (1'b0),                                       // (terminated)
		.reset_in2      (1'b0),                                       // (terminated)
		.reset_req_in2  (1'b0),                                       // (terminated)
		.reset_in3      (1'b0),                                       // (terminated)
		.reset_req_in3  (1'b0),                                       // (terminated)
		.reset_in4      (1'b0),                                       // (terminated)
		.reset_req_in4  (1'b0),                                       // (terminated)
		.reset_in5      (1'b0),                                       // (terminated)
		.reset_req_in5  (1'b0),                                       // (terminated)
		.reset_in6      (1'b0),                                       // (terminated)
		.reset_req_in6  (1'b0),                                       // (terminated)
		.reset_in7      (1'b0),                                       // (terminated)
		.reset_req_in7  (1'b0),                                       // (terminated)
		.reset_in8      (1'b0),                                       // (terminated)
		.reset_req_in8  (1'b0),                                       // (terminated)
		.reset_in9      (1'b0),                                       // (terminated)
		.reset_req_in9  (1'b0),                                       // (terminated)
		.reset_in10     (1'b0),                                       // (terminated)
		.reset_req_in10 (1'b0),                                       // (terminated)
		.reset_in11     (1'b0),                                       // (terminated)
		.reset_req_in11 (1'b0),                                       // (terminated)
		.reset_in12     (1'b0),                                       // (terminated)
		.reset_req_in12 (1'b0),                                       // (terminated)
		.reset_in13     (1'b0),                                       // (terminated)
		.reset_req_in13 (1'b0),                                       // (terminated)
		.reset_in14     (1'b0),                                       // (terminated)
		.reset_req_in14 (1'b0),                                       // (terminated)
		.reset_in15     (1'b0),                                       // (terminated)
		.reset_req_in15 (1'b0)                                        // (terminated)
	);

endmodule
