ac = lui r28, 0x1001
ad = addiu r28, r28, -24528
ae = addiu r17, r29,4
af = addiu r3, r17, 4

ac, ad => WAW
ac, ad => RAW
ae, af => RAW

5 + 4 + 1 + 4 (without forward)
5 + 1 + 1 + 1 (with forward)

0.6893
0.7116

b is out of order

yes, ad has to wait (at least 1 cycle) : be at least 1 cycle behind

ap is the first to be executed ooo
no dependency, it is a jump

important because of interruptions

lw has to wb in a register

a & c have the same performance : this is because c only has more Fonctional Units, which are useless, as the pipeline can only fetch 1 instruction / s

As d can only issue 1 instrution/cycle, and ab is processed, ac nor ad can come in => no dependency

The bottleneck is the issue_width, by setting it to 4, the IPC is now 0.8668

e is faster than b (0.8940)

The common case is 1 instruction / cycle
The bottleneck is the number of FU, by setting it to 4, we achieve an IPC of 1.4055

The buffer is full. change ruu_size to 32

ac is executed 1 cycle after ab, this is a RAW
az is executed before ay, but the reorder buffer reorders

! ENJOY IT !