I)
1. The register file is read in the 2nd of the cycle, because new values are always written in the 1st half of the cycle (integer, fp or loads).
Avantages : (A FINIR)
Disadvantages : (A FINIR)

2. Before the renaming, these 5 bits correspond to the number of the logical register (the register indicated on the instruction written by the compiler).
The mapping maps this register to a physical register (which exists on the processor).
As there are 64 physical registers, due to the fact that the processor needs more physical registers than the number of logical ones,
after the renaming, each register is indicated with 6 bits.

3. 
Queues : The Queues store the instruction which will soon be executed. They use the Busy Bits Tables to know when the operands are ready. They are equivalent to the Reservation Stations in the course.
Active list : This structure memorizes (in order) all instructions currently in the processor. When the Execution Unit in charge of the instruction has finished executing it,
it sends a signal to the Active List, which graduates it (A VERIFIER). It is similar to the ROB in the course.
Register Map Tables : These structures store both register mappings for integer registers and floating point ones, from physical registers to logical ones.
It is equivalent to the register file which contains both the architectural register file and the rename register file.

4.
Rdy : The Rdy field contains 3 bits each indicating if the corresponding register is valid, and contains the correct value.
OpA, OpB, OpC : These three fields contain the number of the physical register which has been translated by the Register Map from the original fields fR, fS and fT.
Dest : This field contain the number of the physical register in which the instruction has to write its result. It has been 'allocated' by the Free List.
Old Dest : It contains the previous mapping of the logical destination register. Thus, this physical register number is used to indicate that the current value in this physical register can be graduated.
Log Dest : This field contain the logical register number of the destination. It is used to detect dependencies.
Tag : This 5 bits field uniquely identifies an instruction.
D : The Done bit is set when a exection unit completes the instruction.

5.
Floating Point Queue : The FP queue stores 16 entries, each of which are 4+4+10+3+6+6+6+6+5 = 50 bits, as indicated on Fig.5.
Floating Point Register Map Table : This uses 32 * (5 + 6) = 352 bits, as it contains 32 mapping from logical to physical.
Floating Point Free Register List : As it stores all unmapped physical registers, it uses 32 * 6 = 192 bits.
Floating Point Busy Bit Table : This structure indicates whether each physical register holds a valid value, it uses 64 * 1 = 64 bits.

6. There are 12 read ports in the FP busy bits table. This is because each of the 4 instructions decoded each cycle can access this structure, requesting for the status of each of their 3 operands.
There are 16 read ports and 4 write ports in the FP register map table. This is because each of the 4 instructions decoded each cycle needs to know the mapping of (at most) 3 operands and 1 destination registers, 
and each of these instruction needs a new mapping for the result of the operation.

7. 
RAW dependencies : These dependencies are detected by first getting the current register mapping, and then checking if the corresponding physical register holds a valid value (by using the busy bit table).
No instruction will be executed unless all of its operands are valid.
WAR and WAW dependencies : As these two are not data dependencies, the processor takes care of them by changing the physical destination register after each new value is written.

II)
1.When an exception occurs for a given instruction, all instructions preceding it in the Active List are discarded.
An important step resides in the fact that the processor must restore the mapping logical to physical register as it was when the instruction was decoded.
This is done by running through the Active List in from the newest instruction to the oldest one until the faulty instruction.
By doing this, it seems to the programmer that none of the discarded instruction has ever been fetched.
The processor must also set the program counter to the faulty instruction.

2.(A FINIR)

III)
1.The R10000 uses a dynamic 2-bit algorithm, and a 512 entries table. Each branch is identified with 9 bits : 11 to 3. Each time a branch is taken, the algoritm increases its entry by 1, and decreases it if the branch is not taken.
It predicts that the branch will be taken if its counter is equal to 2 or 3, and predicts otherwise if its counter is 0 or 1.
(AJOUTER IMAGE)

2.The processor has a 4-entry Branch Stack which is used to store its state when a branch is decoded. This stack contains the adress of the branch is case of a misprediction, which will be the new PC in case the preidction was wrong.
Each entry also contain a copy of both Register Map Tables (integer and floating point), at the time the branch was decoded.
In case of misprediction, similarly to the exception case, all instructions fetched in the Active List after the branch are discarded.
In order to fully remove all instructions depending on the branch, all instruction in the queues and execution units use a 4-bit mask which indicates the branch it depends on. If the branch is mispredicted, the processor uses this mask to remove the instructions.
Unlike the case of an exception, it does not need to run trough the Active List to recover the original register mapping, but uses the copy of the maps which were stored in the Branch Stack.

3.There is a NOP after the branch because in "the Mips architecture, the processor executes the instruction immediately following a jump or branch", and the designers of this processors decided to keep it like this in order to provide compatibility.
If there was no NOP, the processor would execute LD $I1, #0000($I10)
 even if the branch would result in a jump to 'loop'.
We can put the instruction 'ADDI $I4, $I4, 4' just after the branch, and remove the NOP.